1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor memory device which includes a cache memory. A DRAM having a large storage capacity is used as a main memory, and an SRAM having a smaller storage capacity is used as the cache memory and both are provided on a semiconductor chip. The present invention also relates to a data transferring method for the semiconductor device.
2. Description of the Related Art
Generally, a data processing system uses a typical DRAM having a large storage capacity to reduce the cost of the system. However, recently, the operating speed of microprocessing units (MPU) has increased to 250 Mhz or greater. Although the operating speed of DRAMs has significantly increased, their operating speed is much less than the operating speed of today's MPU. Research has been performed in different areas attempting to solve the reduction in operating speed of a data processing system due to the difference in operating speed between the associated DRAM and an MPU. One solution is to use a merged memory with logic (MML) in which a DRAM together with a logic circuit are provided on a chip. A further proposed solution involves installing a DRAM, an SRAM which is a cache memory, and a logic circuit on a single chip. In this latter proposed solution, in which a DRAM, an SRAM and a logic circuit are installed on a chip, a circuit is required for effectively transferring data between the SRAM and the DRAM. However, up to now, no method for effectively transferring data between an SRAM and a DRAM has been developed.